AMD has rethought its roadmap and, given its limited resources and near-death experience with Barcelona, it’s scrubbing Montreal, the eight-core chip that was supposed to follow Shanghai, the chip after Barcelona, and substituting a six-core part code named Istanbul to be followed by a 12-core part called Magny-Cours.

Speculation has also been rife this week that AMD would finally tease out its so-called asset-lite manufacturing plans, some kind of cost-saving outsourcing scheme, at its shareholders meeting Thursday, chatter that has flamed into speculation that it will break in two – a manufacturing business and a chip design and development operation.

It didn’t have a thing to say on either asset-lite, a notion AMD CEO Hector Ruiz first dangled without explaining a year ago, or any restructuring at the meeting. Now there are rumors of a manufacturing announcement on May 15.

Anyway, both of the new chips will use the same core as the hard-won Barcelona quad, a move that could push out Bulldozer, the company’s anticipated shift to a new, next-generation, Fusion architecture that was due in the second half of 2010.

Montreal, which was scheduled for next year, was simply supposed to put two quad-cores in a multi-core package a la Intel.

Istanbul, due in the second half of ’09, is a bit more ambitious. It’s supposed to put six cores on a single piece of silicon all sharing a common 6MB L3 cache, more AMD’s style.

Magny-Cours, due in the first half of 2010, will be Montreal-like but using native six-cores.

Barcelona’s native quad design, while more chi-chi than Intel’s two dual-core processors duct-taped together, has cost AMD its edge, a year in the marketplace and a lot of blood-red ink. The question is: Can it execute Istanbul?

AMD did not disclose how the Magny-Cours cores would be linked. It’s supposed to have 12MB of L3 cache.

There’s another six-core chip on the roadmap called Sao Paulo also due in 2010.

Chip groupie Nathan Brookwood said AMD is trying to be conservative and, given the technology-induced delays with Barcelona, doesn’t want to court undue risk.

AMD “won’t have performance leadership,” he said, “but it should manage to stay within shooting range of Intel depending on how good Intel’s Nehalem microarchitecture turns out to be. It’s still an unknown.”

Nehalem should be good for eight or more cores. Intel is already supposed to have a six-core chip code named Dunnington ready in the second half of this year, a year ahead of AMD’s plans.

Like Montreal, the three new AMD processors will be 45nm and use DDR-3 memory.

AMD is currently sampling its first 45nm processor, Shanghai, which is supposed to be on track for 2H08 production with coherent HyperTransport 3.0 processor-to-processor communication and 6MB worth of shared L3 cache.

Istanbul is supposed to fit in the same chipsets as Barcelona and Shanghai, using the same memory systems, power and cooling, a safe track.

Apparently the eight-core Montreal wouldn’t have produced as high a clock rate as the Istanbul and not all workloads will scale past six cores.

The 12-core part will run slower than the six-core. Parallel workloads are more likely to use it.